Please answer the following questions completely:1)Complete the waveform below given the circuit in Figure 4. For S and R, assume the D-latch is constructed as shown in Figure 3. You may submit a hand drawn waveform.2) If the circuit in Figure 7 utilized the 2-bit ripple-carry adder designed in Lab 3, what would be the maximum value of f given that each gate-delay unit is 4 ns? Assume that the flip-flops are ideal and do not add any additional timing constraints to the circuit.Attachment 1Attachment 2Attachment 31. Complete the waveform below given the circuit in Figure 4. For 5′ and R, assume the Dlatch isconstructed as shown in Figure 3. You may submit a hand drawn waveform. Curfell SimulltlonThu: 33 m 6 ECEN 248 tboratory Exercise #8 7 2. If the circuit in Figure 7 utilized the 2-bit ripple-carry adder designed in Lab 3, what would be themaximum value of f given that each gate-delay unit is 4 ns? Assume that the ?ip-?ops are ideal anddo n_ot add any additional timing constraints to the circuit.

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